Routing Algorithms in Networks-on-Chip

Author: Maurizio Palesi

Publisher: Springer Science & Business Media

ISBN: 9781461482741

Category: Technology & Engineering

Page: 410

View: 793

This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation. Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.
Routing Algorithms in Networks-on-Chip

Author: Maurizio Palesi

Publisher: Springer

ISBN: 1461482739

Category: Technology & Engineering

Page: 410

View: 802

This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation. Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.
Bio-Inspired Fault-Tolerant Algorithms for Network-on-Chip

Author: Muhammad Athar Javed Sethi

Publisher: CRC Press

ISBN: 9781000048117

Category: Computers

Page: 158

View: 138

Network on Chip (NoC) addresses the communication requirement of different nodes on System on Chip. The bio-inspired algorithms improve the bandwidth utilization, maximize the throughput and reduce the end-to-end latency and inter-flit arrival time. This book exclusively presents in-depth information regarding bio-inspired algorithms solving real world problems focussing on fault-tolerant algorithms inspired by the biological brain and implemented on NoC. It further documents the bio-inspired algorithms in general and more specifically, in the design of NoC. It gives an exhaustive review and analysis of the NoC architectures developed during the last decade according to various parameters. Key Features: Covers bio-inspired solutions pertaining to Network-on-Chip (NoC) design solving real world examples Includes bio-inspired NoC fault-tolerant algorithms with detail coding examples Lists fault-tolerant algorithms with detailed examples Reviews basic concepts of NoC Discusses NoC architectures developed-to-date
Analysis and Design of Networks-on-Chip Under High Process Variation

Author: Rabab Ezz-Eldin

Publisher: Springer

ISBN: 3319798375

Category: Technology & Engineering

Page: 141

View: 683

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.
Transient and Permanent Error Control for Networks-on-Chip

Author: Qiaoyan Yu

Publisher: Springer Science & Business Media

ISBN: 1461409624

Category: Technology & Engineering

Page: 160

View: 536

This book addresses reliability and energy efficiency of on-chip networks using cooperative error control. It describes an efficient way to construct an adaptive error control codec capable of tracking noise conditions and adjusting the error correction strength at runtime. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance.
Analysis and Design of Networks-on-Chip Under High Process Variation

Author: Rabab Ezz-Eldin

Publisher: Springer

ISBN: 9783319257662

Category: Technology & Engineering

Page: 141

View: 684

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.
Advances on Smart and Soft Computing

Author: Faisal Saeed

Publisher: Springer Nature

ISBN: 9789811560484

Category: Technology & Engineering

Page: 657

View: 348

This book gathers high-quality papers presented at the First International Conference of Advanced Computing and Informatics (ICACIn 2020), held in Casablanca, Morocco, on April 12–13, 2020. It covers a range of topics, including artificial intelligence technologies and applications, big data analytics, smart computing, smart cities, Internet of things (IoT), data communication, cloud computing, machine learning algorithms, data stream management and analytics, deep learning, data mining applications, information retrieval, cloud computing platforms, parallel processing, natural language processing, predictive analytics, knowledge management approaches, information security, security in IoT, big data and cloud computing, high-performance computing and computational informatics.
Algorithms and Architectures for Parallel Processing

Author: Guojun Wang

Publisher: Springer

ISBN: 9783319271408

Category: Computers

Page: 845

View: 877

This four volume set LNCS 9528, 9529, 9530 and 9531 constitutes the refereed proceedings of the 15th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2015, held in Zhangjiajie, China, in November 2015. The 219 revised full papers presented together with 77 workshop papers in these four volumes were carefully reviewed and selected from 807 submissions (602 full papers and 205 workshop papers). The first volume comprises the following topics: parallel and distributed architectures; distributed and network-based computing and internet of things and cyber-physical-social computing. The second volume comprises topics such as big data and its applications and parallel and distributed algorithms. The topics of the third volume are: applications of parallel and distributed computing and service dependability and security in distributed and parallel systems. The covered topics of the fourth volume are: software systems and programming models and performance modeling and evaluation.
Nature-Inspired Networking

Author: Phan Cong-Vinh

Publisher: CRC Press

ISBN: 9781351182065

Category: Computers

Page: 349

View: 671

"Nature-inspired" includes, roughly speaking, "bio-inspired"+"physical-inspired"+"social-inspired"+ and so on. This book contains highly original contributions about how nature is going to shape networking systems of the future. Hence, it focuses on rigorous approaches and cutting-edge solutions, which encompass three classes of major methods: 1) Those that take inspiration from nature for the development of novel problem solving techniques; 2) Those that are based on the use of networks to synthesize natural phenomena; and 3) Those that employ natural materials to compute or communicate.
Contemporary Computing

Author: Sanjay Ranka

Publisher: Springer Science & Business Media

ISBN: 9783642035470

Category: Science

Page: 662

View: 926

This book constitutes the refereed papers of the 2nd International Conference on Contemporary Computing, which was held in Noida (New Delhi), India, in August 2009. The 61 revised full papers presented were carefully reviewed and selected from 213 submissions and focus on topics that are of contemporary interest to computer and computational scientists and engineers. The papers are organized in topical sections on Algorithms, Applications, Bioinformatics, and Systems.
Sustainable Wireless Network-on-Chip Architectures

Author: Jacob Murray

Publisher: Morgan Kaufmann

ISBN: 9780128036518

Category: Computers

Page: 162

View: 564

Sustainable Wireless Network-on-Chip Architectures focuses on developing novel Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS) algorithms that exploit the advantages inherent in WiNoC architectures. The methodologies proposed—combined with extensive experimental validation—collectively represent efforts to create a sustainable NoC architecture for future many-core chips. Current research trends show a necessary paradigm shift towards green and sustainable computing. As implementing massively parallel energy-efficient CPUs and reducing resource consumption become standard, and their speed and power continuously increase, energy issues become a significant concern. The need for promoting research in sustainable computing is imperative. As hundreds of cores are integrated in a single chip, designing effective packages for dissipating maximum heat is infeasible. Moreover, technology scaling is pushing the limits of affordable cooling, thereby requiring suitable design techniques to reduce peak temperatures. Addressing thermal concerns at different design stages is critical to the success of future generation systems. DTM and DVFS appear as solutions to avoid high spatial and temporal temperature variations among NoC components, and thereby mitigate local network hotspots. Defines new complex, sustainable network-on-chip architectures to reduce network latency and energy Develops topology-agnostic dynamic thermal management and dynamic voltage and frequency scaling techniques Describes joint strategies for network- and core-level sustainability Discusses novel algorithms that exploit the advantages inherent in Wireless Network-on-Chip architectures
Network-on-Chip

Author: Santanu Kundu

Publisher: CRC Press

ISBN: 9781466565272

Category: Technology & Engineering

Page: 388

View: 941

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.